This invention relates to a semiconductor device, a method of manufacturing the same, and a method of processing a semiconductor surface.
Among various semiconductor devices, there is a field effect transistor that will be mainly considered as a metal-insulator-semiconductor (MIS) transistor or a metal-oxide-semiconductor (MOS) in the instant specification and that has a source region, a drain region, and a channel region along a semiconductor surface. In this connection, the following description will be mainly made about the MOS transistor, which is a representative MIS transistor. As well known in the art, such an MOS transistor is classified into an n-type field effect transistor (will be simply called an n-type transistor) and a p-type field effect transistor (will be simply called a p-type transistor).
It often happens that both the n-type transistor and the p-type transistor are integrated in a single chip as a large scale integrated (LSI) circuit. In this event, each transistor is formed on a silicon substance, such as a silicon substrate, a silicon film and the silicon substance usually has a surface with a (100) crystal plane orientation. Such silicon substance and such a surface with the (100) crystal plane orientation may be referred to as a (100) silicon substance (or simply a (100) silicon) and a (100) surface, respectively.
It is to be noted throughout the instant specification that the (100) surface with the (100) crystal plane orientation collectively implies not only (100) surface but also its equivalent surfaces, such as (010), (001), and so on.
Herein, when the n-type transistor and the p-type transistor are manufactured by the use of the (100) silicon substance, it is known in the art that the p-type transistor is as low as about 30% of the n-type transistor in performance (or drivability), such as mobility. Taking this into consideration, it is usual that the p-type transistor is designed so that it becomes large in size as compared with the n-type transistor. However, such designing becomes a bar to miniaturization of a semiconductor device.
Referring to FIG. 1, description will be made for a better understanding of this invention about a conventional method for manufacturing a semiconductor device. In the illustrated example, an n-type transistor of a lightly doped drain (LDD) structure is formed in a semiconductor region.
In FIG. 1(a), a p-type silicon substance 101 is prepared which has a (100) surface with a (100) crystal plane orientation and which may be simply called a p-type (100) silicon substance. As shown in FIG. 1(a), the p-type (100) silicon substance is subjected to a shallow trench isolation (STI) method to isolate element or device regions from others. As a result, the device region is defined or partitioned into the (100) surface of the p-type (100) silicon substance. The silicon substance may be, for example, a semiconductor substrate, a semiconductor layer or film on the semiconductor substrate, as mentioned before.
Next, the (100) surface of the p-type (100) silicon substance, especially, the device region 102 is subjected to RCA cleaning by the use of NH4OH—H2O2—H2O (SC1) and HCl—H2O2—H2O (SC2), as shown in FIG. 1(b). As the result of the RCA cleaning, organic matters, particles and impurity metals are removed from a whole surface. Subsequently, a gate insulation film (SiO2) 103 are formed on the surface (FIG. 1(c)).
As shown in FIG. 1(d), boron (B) is ion-implanted on the whole surface of the silicon substance 101 and ion-implanted boron serves to control a threshold voltage. After the ion implantation, a poly-crystalline silicon (poly-silicon) film is deposited on the whole surface of the silicon substance 101 and is patterned to leave a poly-crystalline silicon electrode 105 on the gate insulation film 103 of the device region 102, as illustrated in FIG. 1(e).
Subsequently, phosphorus of a low density is ion-implanted, as shown in FIG. 1(f), to form source and drain regions 106 of an n-type, both of which are effective to mitigate a high electric field. Thereafter, a silicon oxide film (SiO2) is deposited by a CVD method or the like on both the surface of the silicon substance 101 and on the gate electrode 105 and is selectively etched by anisotropic etching to leave a side wall insulation film 107 on a side wall of the gate electrode 105, as illustrated in FIG. 1(g).
Under the circumstances, ion implantation of an n-type impurity, such as arsenic, is carried out with a high density to form source and drain regions 108 of n+ type, as shown in FIG. 1(h). Thus, the n-type transistor is manufactured by using the p type (100) silicon substance.
A p-type transistor can be manufactured in a manner similar to the n-type transistor by the use of a (100) silicon substance, although not shown in FIG. 1. However, it is to be noted that the p-type transistor is inferior to the n-type transistor in mobility when the n-type and the p-type transistors are manufactured by the use of the (100) silicon substance.
In order to enhance the mobility of the p-type transistor, a proposal has been made about using a (110) silicon substance which has a (110) surface with a (110) crystal plane orientation. Practically, it has been reported that using the (110) silicon substance makes it possible to raise up the mobility of the p-type transistor to about 2.5 times in comparison with the case where the (100) silicon substance is used. However, it has been pointed out also that using the (110) silicon substance brings about reducing the mobility of the n-type transistor by a factor of about 0.6 in comparison with the case where the (100) silicon substance is used.
Under the circumstances, it has been considered that the (110) silicon substance becomes a very efficient material, if it is possible to suppress the reduction of the mobility in the n-type transistor.
Neither suggestion nor proposal has been made at all at the present about a method of avoiding a reduction of the mobility in the n-type transistor formed by the (110) silicon substance.
Various apparatus and methods that might be applied to the (110) silicon substance are disclosed in International Patent Publication No. WO98/33362 (will be called Reference 1) and Japanese Unexamined Publication No. Hei 11-57636 (will be called Reference 2). However, experiments of Reference 1 have been made only about (100) silicon substance but never made about (110) silicon substance. Likewise, Reference 2 has investigated only a (100) silicon substance and never considers a (110) silicon substance.
On the other hand, disclosure is made in Japanese Patent Unexamined Publication No. Hei 9-51097 (Reference 3) about a method of manufacturing a field effect transistor. The method is effective to avoid a degradation of a boundary or interface mobility, which might be caused to occur due to electron scattering on an interface between a silicon surface and an oxide film. However, no investigation is made in Reference 3 at all about (110) silicon substance, although Reference 3 teaches about making a running direction of electrons in the (100) silicon substance parallel with a direction of a step.
According to inventors' studies, it has been found out that, when a field effect transistor is manufactured by the method illustrated in FIG. 1, a surface of the device region is inevitably roughened during an alkali processing step in the RCA cleaning, a rinsing step by pure water, and the like.
Herein, a mobility of a carrier in a field effect transistor is one of factors showing the drivability of the transistor. As well known in the art, a hole is the carrier in the p-type field effect transistor while an electron is the carrier in the n-type transistor. In general, it is necessary to raise up a mobility of a carrier by lessening a surface roughness of the element region so as to improve the drivability of the field effect transistor.
Specifically, it has been found out by the inventors that using usual RCA cleaning brings about roughening the element region of the silicon substance to a surface roughness Ra=0.5 to 1.5 nm, where Ra is representative of an arithmetical mean deviation of surface (i.e., a center line average roughness) and that the gate insulation film is deposited on such a roughened surface.
In addition, the gate insulation film is often a silicon dioxide film that is deposited by using dry O2. In this event, it has been observed that a boundary between the silicon surface and the gate insulation film of SiO2 is further roughened. This would result from the fact that, when the dry O2 is used for oxidation, species or seeds for oxidation are invaded from (111) facets and oxidation preferentially proceeds along the facets.
Moreover, when a field effect transistor is manufactured by the use of a silicon substance that is roughened by the RCA cleaning, a drivability of the field effect transistor is reduced. In addition, when an electric voltage is applied on the gate electrode, an electric field is eccentrically concentrated on minute projections and such concentration of the electric field is liable to bring about breakdown of the gate insulation film.
Especially, when the silicon substance which has a surface (110) with the (110) crystal plane orientation or its equivalents is cleaned by the RCA cleaning, it has been found out that the (110) surface is greatly roughened, which results in a reduction of the mobility when the field effect transistor is manufactured. Although the above-mentioned description has been restricted to the n-type transistor, this applies to any other semiconductor devices, such as TFT, CCD, IGBT, and the like.